(a) Field of the Invention
The present invention generally relates to a word line river for use in a multi-value mask read-only memory device (ROM), and to a method for reading data from a multi-value mask ROM.
(b) Description of the Related Art
Multi-value mask ROM is generally used for storing a large capacity program data etc. in a reduced chip area. FIG. 1 shows a block diagram of a conventional word line driver in a multi-value mask ROM, whereas FIGS. 2A and 2B are a timing chart and a waveform chart, respectively, of the signals in the word line driver of FIG. 1. The word line driver shown in FIG. 1 comprises a word line potential generator 11 for providing a plurality of potential levels, a timing signal generator 25 for detecting an address change in an address signal to thereby generate a plurality of one-shot signals at different timings, and a word line decoder 13 for decoding the address signal to select one of the word lines specified by the address signal. The timing signal generator 25 includes a delay circuit 26 for receiving an original one-shot signal to generate one-shot pulses at different timings. The output of the word line decoder 13 is connected to a word line 14, which is connected to the gates of memory cells 50 arranged in a selected row of a memory unit 51. The word line 14 is connected to the output of the word line decoder 13 and includes a parasitic resistance of several hundred kilo-ohms and a parasitic capacitance of several pico-farads, as shown in FIG. 1.
In the multi-value mask ROM, the different potential levels are provided for read-out of data from a selected memory cell, the different potential levels corresponding to the multi-value data stored in the memory cells. The multi-value data have been written into each memory cell by supplying different levels of writing voltage based on the multi-value data to be stored. The thus stored multi-value data can be read-out by specifying the respective voltage levels with which the data have been written.
Here, an example is given in the figures for reading two-bit data as the multi-value data. In this example, one of a possible set of multi-value data (0, 0), (0, 1), (1, 0) and (1, 1) is stored in the selected memory cell, the multi-value data corresponding to respective writing voltage levels 0, 1, 2 and 3. The relationship between the potential levels generated by the word line potential generator 11 is such that
(source potential)&gt;(second potential)
&gt;(first potential),
wherein the voltage level 0 for writing is set lower than the first potential, the voltage level 1 is set between the first potential and the second potential, the voltage level 2 is set between the second potential and the power source potential, and the voltage level 3 is set higher than the source potential.
In operation, the timing signal generator 25 receives an address signal 100 supplied from outside the ROM, and outputs an original one-shot pulse 101 by responding to the address change in the address signal 100, as shown in FIG. 2A. The delay circuit 26, receiving the original one-shot pulse 101, outputs a first one-shot pulse 102 at the first tap after a first fixed delay, thereby supplying the first potential from the word line potential generator 11 to the source of the P-channel transistor of an inverter 21 in the word line decoder 13. As a result, the potential of the word line 14 rises from the ground potential to the first potential. Here, a time difference arises before desired potential values are attained between the proximal end (106) and the distal end (107) of the word line 14 with respect to the output of the word line decoder 13, as shown in FIG. 2B. The writing voltage applied for the selected memory cell in the fabrication process of the ROM is determined by discriminating the voltage read out from the selected memory cell between the level 0 and a level other than 0. If the writing voltage is determined to be zero, then the stored data is (0,0).
A second one-shot pulse 103 is then generated by the delay circuit 15 at the second tap after a second fixed delay, thereby supplying the second potential from the word line potential generator 11 to the source of the P-channel transistor of the inverter 21. As a result, the electric potential of the word line 14 rises from the first potential to the second potential. The writing voltage for the selected memory cell is determined by discriminating the read out voltage between the level 1 and a level other than 1, if the selected voltage has been determined as a level other than 0 during application of the first potential to the word line. If the writing voltage is determined to be level 1, then the stored data is (0,1).
Further, a third one-shot pulse 104 is generated by the delay circuit 26 at the third tap after a third fixed delay, thereby supplying the power source potential from the word line potential generator 11 to the source of the P-channel transistor of the inverter 11. As a result, the electric potential of the word line 14 rises from the second potential to the source potential. The writing voltage for the selected memory cell is then determined by discriminating the voltage read out from the selected memory cell either the level 2 or a level other than 2, if the writing voltage has been determined as a level other than 0 for the first potential and a level other than 1 for the second potential. This provides the discrimination of the stored data between (1,0) and (1,1). With these operations, it is possible to determine the writing voltage level for the selected memory cell, which is specified by the word line decoder 13 and a column decoder not shown, to read out the written multi-value data.
After the read-out, a discharge one-shot pulse 105 is supplied from the delay circuit 15 at the fourth tap, and turns on the N-channel transistor 20, thereby lowering the electric potential of the word line 14 to the ground potential to prepare for a next read cycle which starts by responding to a next address change.
In the conventional word line driver as described above, in order to attain a higher speed in setting the electric potential of the distal end of the word line to a desired level, enlargement of the dimensions of the word line decoder, lessening of the length of the word line per one word line decoder or other measures is needed because of the difference in the transmission time between the proximal end and the distal end of the word line due to the parasitic resistance and capacitance involved in the word line. The enlargement of the dimensions etc., however, necessitates a large chip area or other problem in the mask ROM.